5G L1 FPGA Design Engineer [rekrutacja online]

5G L1 FPGA Design Engineer [rekrutacja online]

Localization: Wrocław

 

Daily activities

 

As part of our team you will contribute to requirements analysis and decomposition, design, implementation and verification of FPGA IP components for 5G telecommunication system. You will be responsible for creating design in RTL code, verification of IP components in UVM, problems investigations and ensuring quality of provided IP Components.

You will develop extensive knowledge of 5G system physical layer, Nokia hardware platforms and the way our customers are deploying them. You will contribute to develop innovative solutions to address Nokia strategy in the 5G domain and beyond.

This is an offer for regular employees.
 
We work with:
  • Verilog, VHDL
  • System Verilog and UVM
  • Questa, Quartus
  • Git, IDM
  • Linux
  • Artifactory,
  • JIRA
  • Continuous integration systems
Our expectations:
  • Education:  BSC / Engineer /MsC in:  Telecommunication, Computer Science, Electronics or a similar subject
  • Good knowledge of English (both spoken and written)
  • Knowledge of FPGA designs and FPGA EDA tools (Quartus/Vivado)
  • Knowledge of Ethernet standard is an advantage
  • Knowledge of 4G/5G standard is an advantage
  • Knowledge of version control systems (GIT, SVN)
  • Understanding and ability to work with technical documentation for digital systems (microprocessors, integrated circuits, embedded systems)
  • Ability to analytical thinking and solve technical problems

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